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NI9217 FPGA timing

Hi Greg,

Thanks again for the reply!  As for you seeing the same behavior when actually targeting your FPGA device, I am a little confused because I have been able to write a small sample of code myself where I tried to write some samples to the FIFO that would be a larger number than the actual depth of the FIFO and my program is not hanging.  I have created an indicator that goes to TRUE when the FIFO returns a value of true and it appears to be functioning correctly.

As for you getting Error 61003 after the Run command, that is most likely occurring because you are trying to start the execution of your FPGA VI twice.  When you use the Open FPGA VI Reference function, it may be configured to "Open and Run" instead of just "Open."  Then, when you are using the Run Invoke Node later in the program, the program gets confused because you have already told the FPGA VI to run once.  You can check the settings of your Open FPGA VI Reference function by right-clicking it and seeing where the check mark is located in the resulting menu. 

With your question about the remaining number of elements in your FIFO, the size of the FIFO does not necessarily play a role in this part.  For example, if you only write 8 elements to the FIFO and then read all 8 out, then the remaining elements should read 0 since those are how many elements are left in the FIFO that you originally wrote to the FIFO.  The empty elements in the FIFO that you did not write any data to will not count in that indicator for the number of elements remaining.

From what I see looking at your program in the loop where you are trying to "flush" the data in the FIFO, the Number of Elements input to the FIFO Read function has a constant of 1 wired to it, which may mean that you are only reading one data element and then you are not able to exit from the loop because the number of elements left is not getting to 0, which is your exit condition for the loop.

When you are using all of the FIFO Configure, Start, Stop, etc methods, you are correct in that they are not necessary.  For example, you do not need to use the Start Method when reading because the FIFO Read method will automatically start the data transfer from the FIFO to the host.  Another example would be when you are using the Configure method for the FIFO on your Host VI.  This sets the depth of the FIFO inside of the host memory, not of the actual FIFO itself for the FPGA to write to.

I know that you said you read the help files, but have you looked inside of the LabVIEW Help under the FPGA Module?  The detailed help in here is where you can find a lot of information about using the FIFOS and the many methods that you are invoking.  I would also suggest pressing Ctrl+H when you have the function on the block diagram and then clicking on the Detailed Help for the function so you can see a more specific definition of each function you are using.

It also might not be a bad idea to post to a new thread if you continue to have questions since the title of this thread is not really about the FIFO questions that you have.  This way, you will probably have some better luck with help from the community because people that may know a good amount about the FIFOs will notice that a thread is about that topic and could possibly help out.  I hope some of this helps and good luck with your application!

Regards

Noah R
Applications Engineering
National Instruments
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Thanks Noah, I think I will start up a new thread since I have gone through all the help files and resources you've indicated multiple times and things just aren't behaving the way you (and all the help) indicate they should...easiest example is that I write 8 elements to my 15 element FIFO, then read 8 elements, and it says there are 7 elements remaining...anyhoo, thanks again for all your help, it is most appreciated!  Off to remove all those extraneous blocks...

-Greg
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Hi Noah,

I am happy to report that the problem has been resolved! I think it was actually removing that extra run block that did it, though I also removed all of the FIFO config/start/stop blocks as well.  The only constant through all of this has been that run block, however, and after removing it and rebooting/resetting the whole chassis, everything appears to run smoothly (aside from the whole FIFO Full thing).  So thanks again for all your help, you've saved me a lot of time and frustration on this project.

-Greg
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That's great Greg!  I'm glad that you got it working for now and I wish you luck in the future with FPGA and the LabVIEW Environment.  Please feel free to start new threads if you continue to have more questions.
Regards

Noah R
Applications Engineering
National Instruments
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