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Need help in FPGA development (parallel loop)

I’m a new user of FPGA module of Labview and I’m having some problem to implement my specification. I have built a serial communication into the FPGA (RIO7831). This labview code is in two VI (One for Write and One for Read). I need to date each octet from the first byte write until the last byte read. During the protocol, there is always a write action following by an acknowledge of the system (so read action). The counter (500 nanosecond period) must run all the time we have a communication.

So I’m not idea how I can have two loops in parallel (Counter to date and either write or read action)?

Sorry for my English,
Thank you in advance,

Nicolas
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Hi,

This Knowlegde Base document could help you.
Could you attach your VI ?

Regards,
Isabelle
Ingénieur d'applications
National Instruments France
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Message 2 of 2
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