Node "DMA FIFO.Read" takes a lot of processor power

[CyGa]

In my app, I'm using a DMA FIFO to transfer data from the FPGA to my Host. So in the Host, the node "DMA FIFO.Read" is placed in a While Loop without any "wait" function.
According to the node behaviour, the while loop whould run only if elements are available in the FIFO and wait when it's empty...
During the "wait" process, my CPU Usage rises up to 50% (according to the Task Manager)...
Why is that ? Is the code inside the node continuously checking if there are elements in the FIFO ??

[alex07]

Hi zyl7,

Can you send us your vi or a screenshot of you code. Which version of software and drivers are you using and what is your hardware configuration?

Regards, 

Alexandre
NIF -AE

[CyGa]

Hi Alex,
Here you can find the part of the code calling FIFO.read method. Imagine that there is a While Loop surrounding this function, so it's executed as soon as there are elements in the FIFO.
When there is nothing in the FIFO, the execution is waiting for new elements (visible in debug mode : green arrow on the FIFO.Read method) and consuming 50% of my CPU time.
I'm using LV 8.5.1 and RIO 2.1. The RIO board is a 7813R.

[alex07]

Hi zyl7

On the RT FIFO Create vi you used in your host vi, there is a  r/w modes input.
This input let you choose which method you want to use for accessing your FIFO. You can either use polling or blocking mode.

In polling mode, your RT FIFO Read will poll your FIFO continuously until an element is available. The problem with setting your timeout to an indefinite amount of time is that during this polling, the RT FIFO Read increases CPU usage and this is what you observe in your application.

I encourage you to have a look at the RT FIFO Create help there http://zone.ni.com/reference/en-XX/help/370622E-01/lvrtvihelp/rtfifocreate/ to understand how to use the other mode.

Regards,

Alexandre
NIF - AE

[Jimmie_A.]

Hello,

I see that you have questions regarding FPGA DMA FIFOs and not RT FIFOs so the information above doesn't apply for you. When it comes to FPGA and DMA you have three options to implement it.

1) Blocking method - perfect when you know the input/output rate - is when you specify the amount of data you want to read from the DMA FIFO by wiring a constant to the Number of Elements input on the invoke node. The DMA Engine will then try to complete the transfer within the time specified with the Timeout input of the Invoke Node and the DMA Engine will not yield control of the CPU in order to achieve maximum throughput.

2) Polling method - add a shift register to the loop that surrounds the invoke node and wire a constant of zero to it so you initialize the register and then wire from the shift register to the the Number of Elements input of the Invoke Method node. First time you will read nothing, but you should also wire the Elements Remaining output to the shift register on the right side of the loop and then the next iteration you will read the amount of data that is available and then perform this over and over again. This method gives you control over how often polling occurs.

3) Interrupts - make use of interrupts in combination with DMA, will not be as fast as the blocking method due to overhead with handling the interrupt but should lower the CPU usage.

Hope this helps!

[alex07]

Thank you Jimmie,
Sorry for my confusion

[StevenA]

Take a look at this post.  Bassett posted a very good example of how to use DMA and interrrupts to reduce CPU usage  (post 25 of thethread)