Hello all, I am having an issue with FPGA FIFOs. I am performing a Target-to-Host DMA transfer and I have two different configurations that use the same FIFO but have dramatically different resource allocation. In the first case shown below, the FIFO resides in a loop that will be called 1k times every time the while loop executes. In this case, when mapping the slice LUTs used are about 15% In the second case shown below, the FIFO is called once each time the while loop executes. In this case, the estimated resource utilization with respect to slice LUTs is 107%. I guess I don't know why this behavior should be expected. Can anyone explain this to me? Thanks, Matt

Again, take a look at the resource utilization statistics link. You're doing most or all of the math in 64 bits, and the resource utilization grows with increasing bit widths. In particular, logical shift, which you use a lot, is an especially expensive operation, and for a 64-bit value it requires more than twice as many lookup tables as the same operation on a 32-bit value. I suspect the implementation really is a huge lookup table - for each possible input there's a corresponding output. This allows it to be very fast at the cost of FPGA fabric. Other mathematical operations (add, subtract, multiply) are more space-efficient. The entire block of logic in the lower-left corner of your VI is an easy candidate to wrap in a single-cycle timed loop, which may save you some space, although it will save mostly flip-flops and not look-up tables.

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Not sure I am understanding FPGA FIFO resource allocation

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Hmmmm...looks like lowering the resolution and replacing the "Replace Array Subset" with "Build Array" where possible has done the trick. Thanks a lot, Nathan.

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Not sure I am understanding FPGA FIFO resource allocation

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