PXI 7966 with NI 5752 digitizer overflow issue

[MansoorEE]

Hello, I am using NI 5752 with NI 7966 to write samples in FIFO from 16 channels at the speed of 50MHz by using timed loop. I am using 4 FIFOs each size 65355 and writing 4 samples into each FIFO at every loop execution and write the total of 2000000 samples in each FIFO 500000 from each channel. When I read those FIFOs on the Host, I don't get all the samples that were written in the FIFO. I think there is a time out issue on the FPGA FIFO. Can someone help resolve this issue?

[Deagle]

MansoorEE,

Is the timeout output of your DMA FIFO at any point returning true? Looking at this guide, page 84 shows one way you can monitor this "Timed Out?" indicator. That section has some good pointers for ensuring lossless data transfer. You may also want to take a look at the High-Performance RIO Developer's Guide.

Thanks,