Pass LabVIEW FPGA block ram address to CLIP node?

[Michel_Gauvin]

Hello,

I need to pass a LabVIEW FPGA block ram memory index to a CLIP node so the CLIP node have access to the data in the BRAM.  The CLIP node contains an IP that we have developped and the IP is using the Xilinx BRAM driver to access data.  I guess that we have to pass the physical address of the BRAM to the CLIP node.

Is this possible? If yes, how? If not, what would be an alternative?

Thanks,

Michel

[Michel_Gauvin]

Hello,

Will the "Distributed Memory Generator" do the job?

Thanks,

Michel

[JDragon]

Hi Michel,

What hardware are you using? Is it a FlexRIO?

Here is a link to a tutorial using CLIP: http://www.ni.com/tutorial/7444/en/

[Dragis]

Michel, can you give a bit more detail on how your system is setup? You say LabVIEW FPGA Block Ram, so I assume that is a Memory resource you configured to use Block Memory. You also mention a BRAM driver which sounds like it's a component that interacts with a Xilinx Block Memory component, possibly generated by Block Memory Generator.

Currently, LabVIEW FPGA does not directly give CLIP nodes access to resource references. Instead, you will need to bring those internal CLIP signals as ports on the CLIP node and then within the LabVIEW FPGA G code you'll need to use those lines to control calling Read and Write methods on the Memory resource. Generally these designs will have a loop that is used solely for this purpose, but there are a number of ways to fit this pattern into an existing design.

Alternatively, you could instantiate the Block Memory inside your CLIP and route any information you need from the LabVIEW FPGA G diagram into the CLIP. Exactly which way is best depends on the specifics of your application.

[Michel_Gauvin]

Hell Dragis,

I'm using a sbRIO-9651 with NI carrier board.  My collegue as developped an IP that I want to use but it has a Dual RAM address (build with "Distributed Memory Generator" in Xilinx Vivado) has one of it's input port.  Bassically his IP needs to read the BRAM at the provided address by the LabVIEW FPGA, so I need to create that BRAM in LabVIEW FPGA and pass it to his IP (which I've putted into a CLIP).

So I want to know if this will work if I use the "Distributed Memory Generator" from Xilinx IP palette in LabVIEW FPGA and pass the address from that IP to the CLIP?

Thanks,

Michel

[Dragis · Accepted solution]

If I understand you correctly, yes, you should be able to use the Block Memory Generator from the Xilinx Palette in LabVIEW FPGA and within the Single-Cycle Loop connect the ports of that block to the CLIP signals exposed by the your colleague's IP. You may need to tweak/adapt some of the signals slightly for LabVIEW dataflow.

[Michel_Gauvin]

Good, I will try it probably at the beginning of next week and will post my results.

Best regards,

Michel

[Michel_Gauvin]

I made a simple example and it worked.  The IP manages the read/write of the Distributed Memory. Thanks for the help.

[Dragis]

Thanks for sharing, I'm glad it worked!