Period unit in FPGA timed loop

[02Fede69]

Hi all,

Could anyone tell me wich is the period unit for a timed loop in FPGA

when I use the default clock?

The context help window says:

"The unit of the period changes depending on the timing sourceyou select".....That's it?

Thank u

Federico

[Jimmie_A.]

Hello Federico!

The default clock on our FPGA targets is 40MHz i.e. 25 ns. One can create derived clocks from this base clock and use them together with the timed loop if needed.

Hope this helps!

[02Fede69]

Hi Jimmie,

Thank u for answering, but what I wonder is:

In order to have a period of 50 ns, Do I set the period input of the timed loop to 50 or to 2? In other words

wich is the unit? ns or ticks?

Federico

[Jimmie_A.]

Hello Federico!

When using the 'Single Cycle Timed Loop' (SCTL) as it is called on FPGA targets i.e  the structure that looks like a timed loop on other targets, you cannot set the period. You don't have access to such an input since the only inputs that are available are:

• Source Name
• Error

On other platforms such as Windows when using the Timed Loop you have the option to specify a period through an input but not when using the SCTL on FPGA targets.

So if you want the SCTL to run with 20 MHz you can either create a derived clock with that frequency or program an internal counter/timer using the base clock.

Hope this helps.

[02Fede69]

Great Jimmie,

OK, thank you very much

Ciao

Federico

[Jimmie_A.]

Great that I could help!

Take care,

[Nick_Kimber]

Sorry to jump in, but I'm still confused by this. My Timed Loop, in an FPGA project, still shows period as an input.