Periodic CAN messages with cRIO 9072 and 9853 CAN module

[efuentes]

Hi,

  I'm a new to LabVIEW and am using LabVIEW 2009.  My project requires that I send multiple CAN messages with different delays (8, 48, 96,100 and 1000 ms).  I planned to do this using the FPGA embedded in the cRIO.  The problem that I am running into is that the instructions aren't carried out fast enough to keep in time.

I have a loop that runs with on a 1 ms timer.  I increment a counter every iteration until it gets to 12 seconds or 12000 ms (the least common multiple of the intervals).  I find which messages need to be sent in the current iteration by subtracting multiples of the delays and checking if the remainder is equal to 0.  For test purposes, if a message needs to be sent, a zeroed out CAN frame is sent.  When I run it, the first few iterations work fine, but it quickly slows to a crawl.

I have done some tests and it takes about 10 microseconds for a message to be sent.  In order to double check, I sent a worst case of 16 messages and it took 163 microseconds, so it doesn't seem to me like this would be the bottleneck.

I have attached my code and would appreciate any help I can get.

Thanks,

Erick

[Joe D.]

Hi Erick,

Would you mind zipping up your project and all the vi's so I can take a closer look at this. CAN on CompactRIO can be a little tricky. I just want to better understand what you are trying to do.

[efuentes]

Not a problem, I have attached it.

[Pcorcs]

Hello,

I believe the performance issue you are facing is due to the fact that you are viewing an FPGA "Front Panel" at run-time. FPGA VI's do not possess a true Front Panel for UI, as they are intended to run as a fully embedded object at many MHz. The FPGA Front Panel is a network manifestation of the I/O operations defined in the FPGA bit file. This module is designed to run on the FPGA target as an embedded communication hub. 

To interact with CAN messaging, typically a 2 FIFO's are required a Target to Host for frames received, and a Host to Target for messages written to the CAN controller. In order to properly evaluate the system I/O we must eliminate the network dependency, as the system will attempt to buffer the information received from the FPGA, and display it when Windows catches up. Ergo, the first message looks good, but suddenly all operations seem to ebb. 

I would recommend developing an RT VI with DMA FIFO, and a state machine architecture for Read/Write control of the 9853. Also, you may attempt to implement your timing requirements in a pre-built LabVIEW example.

Please post back any further questions, or results of this configuration change.

Thank You,