Problems getting started with LabVIEW FPGA

[monguin61]

Two (probably) related questions:

1. I am trying to get started with LabVIEW FPGA, and I am having trouble using a host VI to test my FPGA VI. I started with a basic QAM modulator VI, to be run on the FPGA, and I have reached the point where I need to verify the logic and timing with this VI running on the development computer with simulated IO. I have tried various combinations of putting the code inside single-cycle timed loops vs not; putting the modulator block directly into the host VI, and using the "FPGA reference" block. When neither the host VI nor the modulator VI use a single-cycle timed loop, I see correct behavior. In every other case, the output of the VI is either absent or incorrect. I need to use a single-cycle timed loop in the FPGA VI to properly verify timing behavior (as far as I know), so the one functioning case is not enough for me.

I'm sure there is a key step I'm missing or misunderstanding, but I have not been able to figure it out myself yet. I've attached my modulator diagram as well as two different attempts at host VIs. I can share other information, but I'm not sure what is most relevant.

2. I am also trying to test a simple wrapper VI for the Xilinx FFT block, and I am having trouble accessing FIFOs inside the host VI. I thought this would be relatively straightforward, but when I tried to change the "method" on an "invoke method" block, there were no options for accessing FIFOs, as I understood there should be. This is a total roadblock for me. These two diagrams are also attached, the test diagram shows the options available to me for the "invoke method" block.

Labview 2013, PXIe-7965R, PXIe-8133 controller. 

I had to combine the diagram images; in case they are hard to follow this way, see the individual images here: http://imgur.com/a/oB6OD .

Thanks in advance for any suggestions.

[fromm8]

Hello Monguin61

If you are having problems reading from DMA FIFO's you should test them using a very simple code to understand their behavior. First, you could start taking a look to the linked documents:

Reading DMA FIFOs from Host VIs (FPGA Interface)

Using DMA FIFO to Develop High-Speed Data Acquisition Applications for Reconfigurable I/O Devices

FIFO.Read (Invoke Method)

Then you could test and analyze a simple example to understand how it works, for example this one: Simple DMA FIFO Example for FPGA.

Check the references when you are using DMA FIFO's, I noticed you did not connect them in the second picture attached.

Regards

Frank R.