Problems with FIFOs in FPGA lock in amplfier program

[Eric1493]

Hi,

   I'm trying to program a lock-in amplifier in FPGA. I'm encountering an problem where the "function not ready" indicator lights up in the host when I try to run the FPGA program. This means that the phase lock loop functions are not working for some reason. After waiting for a little bit I get an underflow indicator, which means that the FIFO read in the FPGA isn't receiving any data. I believe what is happening is that the FIFO isn't passing data from my DAQmx card to the FPGA, which is what is causing the "function not ready error." However, I do not know how to go about fixing this FIFO/DAQ error. Could someone check out my code and see what they can make of it? You should look at the LIA_HOST file under the project file first.

Thanks very much,

        Eric

[Pcorcs]

Hello Eric,

Have you run this application with Highlight Execution on the Host? Does the DAQmx Read pass the expected data to the FIFO? Is the timeout case being reached causing the FIFO to abort its execution? 

I appreciate your time working through this issue. We also might find more involvemnt on this thread, if it were posted in a more specific area (i.e DAQ or FPGA) depending on the nature of the issue. Users with more pointed hardware experience, and sometime members of the R&D team, will browse the specific product areas. 

Cheers,