Programmatic item selection of FPGA Read/Write Control?

[karsten281]

Hi,

I have a question about the FPGA Interface Read/Write Control node.

When creating the host VI, one has to select the FPGA controls/indicators which are going to be written/read through FPGA R/W node. Is there any way to select these controls/indicators at run-time? In case this behavior of the FPGA Interface Read/Write Control node is fixed, is there any workaround?

Regards,

Karsten

[GerdW]

Hi Karsten,

why do you want to have such a behaviour at runtime?

When you want to read/write different FPGA controls you could use case structures in your RT host…

[karsten281]

Hi Gerd,

Thank you for your quick reply. Of course, your suggestion is an option and probably I will end up with it if there is no workaround.

The setup connected to the cRIO will be changed from time to time but it will always consist of the same types of components (mainly valves, pumps and heaters). My thought is to have standard labels of controls in the FPGA VI (like Valve[i], Pump[j], Heater[k]) and to have the RT part configurable through an ini file. In this case I would avoid to rewrite the RT host VI when the setup and the FPGA VI are changed.

Kind regards,

Karsten

(Another way would be to use scan or hybrid mode with shared variables, but then it is not possible to have safety functions on the FPGA level.)

[GerdW]

Hi Karsten,

The setup connected to the cRIO will be changed from time to time but it will always consist of the same types of components (mainly valves, pumps and heaters). My thought is to have standard labels of controls in the FPGA VI (like Valve[i], Pump[j], Heater[k]) and to have the RT part configurable through an ini file.

Yes, that's the way to go. Create a FPGA VI maintaining "generic" I/Os with names like DigOut0…n or AnalogIn0…n. Which I/O pin is used for which hardware device is handled mainly in the RT part using a lookup table or any other algorithm you like to use. I do that with all of my cRIO systems…

[crossrulz]

The problem with trying to make FPGA code configurable is that FPGAs are hardware.  Everything must be set.  You can do some things with the FPGA interface to make it more generic, but you will also be limiting what you can do with them.

If you want truely generic code for your RT, then use a DMA FIFO to send commands down to your FPGA.  I typically use a U64 data type with bits packed in to represent the command and data.  The FPGA can then process the command however it needs to and react accordingly.  You can do something similar for the data reading.

[karsten281]

Thanks to both of you. Good to know that there is no real option which I just was not aware of. Probably I will end up with some case structure in the RT host VI.

Regards,

Karsten