Pull frequency & pulse width from Boolean stream of data

[Idratherberacing]

So I have (3) single ended PWM signals coming back from a UUT.  In my FPGA VI, I store these in a U8 to save space and and export them to the HostVI for processing.  My question is: How can I pull frequency and pulse width from each of these signals?  I know I have to split them back up out of the U8, but what's the best way to get those two types of information from each signal in the HostVI??

[David_L]

If you know what the time difference between each bit, you simply can calculate the frequency and pulse width using simple multiplication.  If the time difference is not the same between bits, then you might have to reconsider the way you send data back to your host.

[falkpl]

If you are just interested in the signal timing why dont you implement a counter for each channel in the FPGA and transfer the pulse width information (clock cycles high and low).

For each digital line, keep the shift register value of the last value, on low to high or high to low transfer the count, if no transition increment the channel count, and reset on an edge (where the prevous signal != current signal).  Run this in a sincle cycle timed loop and you will have great time resolution.

[Idratherberacing]

I was just going to say that's how I ended up doing it.  I used a single cycle timed loop and simply counted the ticks...  I just had to sit down and stare at it for a bit.