I have construct 2 LUTs with size 128 bytes (90elements) each in LUT inside the while loop.
And I also used some 2 analog outputs and 2 digital outputs in a while loop and, 3 digital inputs inside the timed loop.
And it displayed that there is a shortage of the FPGA resources.
Before adding those, the code already consumes 99% of slices of the FPGA. I suppose the FPGA will automatically optimise the resoureces of the slices to make it <100%.
However, this time, the limitation is not due to slices, it is mainly due to the number 4 LUTs. In the compliation report, it shows that there is a little bit overuse of the number 4 LUTs..
Can I solve the problems by reducing the half of the size of the LUT?
Here is the compile report
Status: Compilation failed due to resource overmapping.
The FPGA VI does not fit on the FPGA target because the VI requires more resources
than are available.
Suggestions for eliminating the problem:
* Reduce the amount of logic in the VI
* Reduce the number of multiplications, FIFOs, and/or amount of memory on the block diagram
* Change arbitration settings
* Use Timed Loops instead of other loops
* Use Timed Loops for resource-intensive sections of the block diagram that
do not require any looping
* Recompile
Number of 4 input LUTs: 29,497 out of 28,672 102%
