Questions about the High Throughput Math Functions

[zyb1003]

Hello. thanks for replying!

The reason I wire so many complicated stuffs is because I don't know how to wire FPGA VI reference in, error in, and the 4 ports of FIFO Read (number of elements, timeout, data, elements remaining) in this host VI. You say that I need try to use only one FIFO, but this project needs more than 1 FIFO, even 64 bit is not enough too. The reason I split the VI reference is because I think the second FIFO also need a reference in, otherwise, I don't know how to deal with this. If you can tell me how to wire the FIFO read more specifically in this project, that will be good.

Thank you!

[BauerPower · Accepted solution]

Hi! So it would be difficult to try and teach all of the necessary concepts over the forum, so I'd recommend taking a look at some of the developer guides that we've put together for LabVIEW FPGA. The two I'd recommend are

• The High Performance FPGA Developer's Guide, which is mainly focused on high-speed instrumentation like our FlexRIO hardware. That guide contains a section on "TRANSFERRING DATA BETWEEN THE FPGA AND THE HOST SYSTEM"
• The CompactRIO Developers Guide is more focused on our compactRIO hardware, but spends more time covering the basics.

To this specific question, you can use the same FPGA reference wire to provide a reference to all of your RIO host interface functions - you just need to have them in series, one after the other. Using the DMA FIFOs should be pretty well documented in Section 3 of the CompactRIO Developers Guide.

[zyb1003]

Hello, 

I have read the material you provide for me, it's useful and thank you so much. However, there are still some problems. 

I built the host VI analog input loop as following pic, I make two FIFO wired in series, and the FPGA-to-Host 2.read (FIFO2) can read data continually, it is good. 

Then, I want to put the data that the FIFO2 read into the analog output loop of the host VI. That is like transfer data between loops. I know that the local variable can only transfer limited data, so it doesn't work. And I think if I want the data in another loop can output continually, I may still need FIFO and stream.vi. Actually I don't understand stream.vi that thoroughly, is it a must if I want to read data continually? 

I built the FIFO in the analog output loop as following pic, I know it's not correct, but how to fix this? Do you have any good advice for this problem? 

Thank you. 

[ewang52]

Here is a couple of ways to transfer data between FPGA and host.

http://zone.ni.com/reference/en-XX/help/371599F-01/lvfpgaconcepts/pfi_data_transfer/

Streaming is probably the best way for lots of data.

What exactly are you trying to fix in the AO?

Best,

Eric

Applications Engineering

[MyrzaMBM]

Hello
I'm working on a project based on the example getting started 5783 like you.

My problem is that when I compile by referring to the bitfile, the project works perfectly, but when I refer to the VI without changing anything, I have an error in the stream on the AO loop.

I tried to do some modifications in the FPGA VI and compile to have a new bitfile, the project don't work by refering the new bitfile.

It only works by referring the bitfile by default ! 

what can be the problem ! 

thanks

[RavensFan]

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