RIO Scan Interface Watchdog

[bdiesel]

Good Day All,

Is there a way to use the FPGA Watchdog when using RIO Scan Interface?  Ideally I would like to put the outputs of the RIO into a safe state if there is a failure, but I don't really want to have to write the FPGA code to do so.  My scan rates are only of the order of 10ms, so I am not constrained from a performance perspective.

Bruce

[AlastairUK]

Hi Bruce, 

Unfortunately, we can't implement the watchdog functionality on our RT VI as this isn't how it is designed to work. 

The watchdog is designed to check to make sure the RT application and OS is running without failure, meaning the watchdog needs to be able to run independently of the RT application. As we need the utmost reliability with this functionality it is only going to work on the FPGA. 

If you are looking for something similar then maybe check out the link below which looks at Heartbeat applications.
https://forums.ni.com/t5/Example-Programs/Real-Time-Heartbeat-for-VIs-amp-Executables/ta-p/3516410

Thanks, 
Alastair

[bdiesel]

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@AlastairUK wrote:

Hi Bruce, 

Unfortunately, we can't implement the watchdog functionality on our RT VI as this isn't how it is designed to work. 

The watchdog is designed to check to make sure the RT application and OS is running without failure, meaning the watchdog needs to be able to run independently of the RT application. As we need the utmost reliability with this functionality it is only going to work on the FPGA. 

If you are looking for something similar then maybe check out the link below which looks at Heartbeat applications.
https://forums.ni.com/t5/Example-Programs/Real-Time-Heartbeat-for-VIs-amp-Executables/ta-p/3516410

Thanks, 
Alastair

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Hi Alistair,

Thanks for the answer.  I suspect I didn't ask my question properly.  What I am referring to is the RIO Scan Interface having a watchdog function.  My understanding is that the RSI is a standard bitfile that runs on the FPGA and makes all the IO channels available via tags updated at the specified scan rate.  I was wondering whether the RSI provided a watchdog function that would enable it to set all outputs to a safe state (e.g. 0 for AO and false for DO) if the watchdog does not get petted by the RT application.

[EDIT]  If such functionality is not available, what would be the best practice for setting the outputs into a safe state when there is a problem in the RT application in Scan Mode?

Bruce

[AlastairUK · Accepted solution]

Hi Bruce, 

Thanks for the speedy reply, sorry for the misunderstanding! 

From what you have described it isn't going to be possible. The RSI doesn't have that sort of functionality unfortunately.

I have linked below a slide deck with some best practices which may be of help, but ultimately, if you are looking for full control over your outputs to ensure a safe state you will have to code the outputs on the FPGA and not use the scan engine.

http://southafrica.ni.com/sites/default/files/7%20Best%20Practices%20for%20Architecting%20Embedded%2...

Best regards, 
Alastair

[bdiesel]

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@AlastairUK wrote:

Hi Bruce, 

Thanks for the speedy reply, sorry for the misunderstanding! 

From what you have described it isn't going to be possible. The RSI doesn't have that sort of functionality unfortunately.

I have linked below a slide deck with some best practices which may be of help, but ultimately, if you are looking for full control over your outputs to ensure a safe state you will have to code the outputs on the FPGA and not use the scan engine.

http://southafrica.ni.com/sites/default/files/7%20Best%20Practices%20for%20Architecting%20Embedded%2...

Best regards, 
Alastair

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Thanks Alistair.  Am trying to build a generic application, so as to avoid coupling the RT Code tightly to the FPGA code - and I was thinking that it is probably easier to do that via the scan interface as it would be easier to change the type and order of modules in the chassis, but still be able to get the controller in to a safe state if there is a failure.

Thanks for the link, I'll take a look at that!

Bruce