RT HOSR VI and FPGA vi communication

[nathand]

I don't see any obvious efficiency issues with your code.  What I meant by timing mechanism was whether you're using a timed loop, a wait statement, or a timeout somewhere (for example on the FIFO read) to set the loop cycle time.  Here are a few minor things you could do but I don't think they'll result in a noticeable speed improvement:

1) instead of using a separate FPGA Read/Write node, use a shift register to store the value of SENSOR LIMIT, then write the shift register value along with all the other booleans in the first FPGA Read/Write.

2) Use the multiple channel version of Power Spectal Density, since you're using the same parameters each time.

You could also experiment with using a single FIFO and decimating the array to get your two independent signals; LabVIEW can handle decimated arrays efficiently in some cases.

Try using the VI profiler, the Distributed System Manager, and the Execution Trace Tool to identify the slow points in your code if you're still having problems.  Also, as others have suggested, you can write a separate user interface VI and transfer only the data you want to display, which will be more efficient than using a remote front panel.

[suni]

Hi

Thanks for your reply.

" Also, as others have suggested, you can write a separate user interface VI and transfer only the data you want to display, which will be more efficient than using a remote front panel." Do you mean a windows pc host vi. by seperate user interface vi. In that user interface vi not only i am displaying data also writing values to FPGA vi controls. In not very clear how i can have these controls by using seperate user interface vi.

[nathand]

Yes, write a separate VI that will run on your Windows PC and communicates using shared variables or TCP/IP with your RT system.  The communication can go both directions (from the RT system to the PC, and vice versa).  The template that Jon S. recommended demonstrates this.