Rational Resample on FPGA

[ogk.nz]

I'm sure hoping someone on the forums can help me with this as I have been banging my head against it for a couple of days now and making no progress. There is not a lot of information about the "Rational Resampler" Express VI for FPGA on the net that I could find.

Issue is when trying to re-sample data from an accelerometer card down to a lower rational rate for more convenient FFT conversion. We are trying to go down from 10240Hz to 8192Hz and are getting some unexpected behavior.

FPGA Resampler Loop

 Timing in the above case appears to be 4096Hz rather than the expected 8192Hz. In a similar test case we have replaced the "AND Array Elements" with the bool array out of the FOR loop with an "OR Array Elements" and the frequency is showing up as 10240Hz.

This would all seem to indicate that the "Rational Resampler" Express VI is behaving in an odd manner. I figured that since there was the same number of incoming samples being rewritten to the same number of outgoing samples all samples would be getting a valid output at the same time but that doesn't appear to be the case here.

Has anyone had any experience with the handling of samples from the "Rational Resampler"?

[nath05]

Hi,

I found some information that you might find helpful

An Introduction to High-Throughput DSP in LabVIEW FPGA - http://www.ni.com/white-paper/13698/en/

Scheduling Timing Using Handshaking Signals (FPGA Module) - http://zone.ni.com/reference/en-XX/help/371599P-01/lvfpgaconcepts/fpga_handshaking/

Rational Resampler Express VI - http://zone.ni.com/reference/en-XX/help/371599L-01/lvfpga/rational_resmpler_fltr/

Rational Resampling (Digital Filter Design Toolkit) - http://zone.ni.com/reference/en-XX/help/371325F-01/lvdfdtconcepts/rational_resampling/

I hope that this can help you a bit!

[ogk.nz · Accepted solution]

Thanks for the information. I had already found most of that but was still helpful.

I eventually managed to figure out the source of my issue. In the development of the non-single cycle loop version of the "Rational Resampler" I had assumed that when using the indexed version due to the nature of the process the output values would be getting on the same cycle of the loop.

Apparently this is not the case, so in order to the pass the data into the FPGA in a consistent manner I had to buffer the data coming out of the resampler until a full set of valid data points was recorded and then pass that collection of elements to the FIFO.

[hsw9797]

Hi now i have to upsampling to emit sound but there is no information about resampler 

Can i want to your example Vi?

or When i have to upsampling 3 times, when i put one sample to resampler VI the output produce 3 sample as vector?

[ogk.nz]

If you attempt to set a Resample rate greater than 1 (L > M) you will see a couple of changes to the Express VI configuration as it will be forced into 'Single-Cycle timed loop' mode. 

This means that you now need to make use of the following:

• Inputs:
  
  • Input Valid: Specifies whether data at the input is valid. Use to signal when a new known value is available
  • Ready for Output: Specifies whether downstream nodes are ready for data. Use to signal when you are ready to receive new data from the resampler
• Outputs:
  • Output Valid: Returns true if there is a value available for downstream use. Use to know if a value is available
  • Ready for Input: Returns true if ready to receive data. Needed to manage the flow of data into resampler

All of this functionality is not needed in my VI because I was running in 'Outside Single-Cycle'. 

Additionally, this information should indicate that there is no way to configure a resampler to return data as a vector. You will have to do that yourself. 

[hsw9797]

Thank you for your reply

i can't understand process of resampler

i know as interpolation is that obtaining sample and zero padding and apply low pass filter 

because of resampler is black box, i can't understand why VI need input output valid node and other things.

and what happens? if there is silghtly difference sampling rate that differ what we set in resampler VI between RT and FPGA?

Here is my FPGA 

ex i send sine data from RT to FPGA and emit sound from speaker 

2000Hz (RT) -> 25600Hz (NI data rate).  L = 64, M = 5

in RT, i send one sample data to FIFO with rate 2000Hz using Timed Loop. 

but is not work.......

what is the problem.....

please help me.... 

[ogk.nz]

Rational Resampling is not the tool that you need to be using here. 

The purpose of resampling is to populate a waveform with information that can be inferred from a source signal with a different frequency. 

As far as I can tell, the issue that you are having is that you are trying to use a FIFO to send data to a speaker at a rate that is slower than the update rate of the speaker.  Again, while this is not the ideal solution, this can be achieved using the below example. 

The operation of this is pretty straight-forward. Every cycle the speaker gets a value set, if there is nothing in the FIFO then it uses the last value, otherwise it reads the first element from the FIFO. 

[hsw9797]

Thank you, i solved this problem using analog low pass filter. because this problem is same that interpolation.

i think if i use your example. the problem can be more simple. 

Thank you