Real Time Vi Stuck

[Mudda]

Hello,

          I am new to Real Time applications and I am having lot of issues with cRio and FPGA. I made an application for PXI non real time application and modified that for crio and fpga. I had lot of trouble in under standing programming. Now I made a very very simple program for FPGA and also for host system. I am attaching the screen shots of two vi's. the problem is the host vi is going into some lala land and when i click on indicator or if i put a probe on the block diagram it is comming back to the loop and executing for a while and going some where again. I do not know what's going on.

I have another issue. every time i open the project I have to compile the fpga vi even though i did not make any changes to it. My host vi when i try to deploy it to the crio it will not be responding for a while and then comes back live and deploys the vi.  i appreciate if any one can shed some light over these issues. I am using labview 8.0.

Thanks,

Mudda.

[Mudda]

Hello,

            I found out something interesting here. I put  a loop iteration indicator on the fpga vi and i wired that on my host vi. what i ofund out was when my host vi was stcuk the fpga vi was running in the backgournd so i think its my HOst which has a problem the fpga vi is running ok. why would the host vi stuck?

mudda.

[Efosa O.]

Mudda hello.

It seems you are running into a few problems here with programming your cRIO application. What cRIO hardware are you using? Also, I am not exactly sure what you mean when you say "when my host VI was stuck the FPGA was running in the background." How do you know your host VI is stuck? Are you viewing the iteration terminal on the FPGA VI from the host application? If so, does the indicator on the host increase? If it does, then your host VI cannot be stuck.

In regards to compiling everytime you open the project, this should not be the case. What happens when you try and run the FPGA VI? Do you get an error? Do you get a message that says you explicitly need to compile the VI? In some cases, you will get asked if you want to use the old FPGA bitfile or if you want to recompile. In the case where it asks, go ahead and select Use exisiting bitfile then navigate to where that bitfile is saved on your computer.

Please let us know how things are going.

Efosa O.
NIAE.