03-17-2010 01:34 PM
Hello,
I have been given a project to develop a SPI interface with 7 bits of address with one bit to mode (R/W) but the test registers only being 5 bits wide. Is there a way to get the subVI's for the USB-8451 SPI interface to limit the number of bits in the data stream? Or can you release the chip select so that only 5 bits are sent. If anyone has had some experience with this please let me know if this is possible.
Gary Tyrna
Solved! Go to Solution.
03-17-2010 02:27 PM
03-17-2010 04:26 PM
03-17-2010 05:29 PM
ggaryt wrote:
Thank you for your response to my question. Unfortunately I can't bit-bang this because of the operating speed of 50MHz.
Well that's a wee bit of an important fact.
NI only has 1 SPI device. I am not aware of third-party SPI devices that can operate at that speed, let alone control the number of clocks.
I'm not all that familiar with the FPGA, but the basic spec for the NI LabVIEW FPGA Module is a loop rate of 40 MHz. You may need to look into some of the high-speed digital devices that NI sells. My suggestion is to contact your local NI sales rep.
03-18-2010 10:43 AM
Yea that is a bit of important infomation.
Talking this over with my boss we have come up with a possible solution by sending the data stream as 16 bits (wants 13) which will cause the interface to believe the address sequence is restarting but we have a way of reinitializing the input so it will sync back up. He is also trying to get the customer to go to a more standard format I hope.
Thanks for you help.
Gary Tyrna