Refilling Host to Target DMA FIFO on cRIO

[Cvok]

FIFO is big enough, with Configure method I set the size of FIFO to be equal to array size + 1. 

I've attached the current code which I'm testing on Windows right now. Basically I have N number of files (e.g. 10) which do not change, and I need the data from 1 file at a time to be written to FIFO and read at FPGA. Because of problems given by last code with losing communication while handling large data I have moved the reading from file part in a Frame before the "main timed loop" (produces "ucitaj" boolean which triggers writing to FIFO).  I've placed this code in a For loop to read all files and store data in Array1 which is then wired into the next Frame. Next Frame contains main timed loop(not shown) and a parallel while loop with Case structure (fig. 2) which indexes a subarray from Array1 (each file represents 1 row), and passes the subarray to the FIFO write then FIFO is empty (Empty elements remaining greater than..  & "ucitaj" = T). What are the timing limitations of this design? I've placed wait to be sure that the code is executed, because I believe that large files need more time to be read, stored in array and be read again?