Hi all!
I'm working on a school project trying to collect data from an accelerometer with an NI 9201 module in a cRIO 9074 chassis. In Labview 2011 I wrote an FPGA VI which collects data to a FIFO and a RT VI which reads this data from the FIFO, displays it on a chart and saves it to a .tdms file on the cRIO. The problem is that I can colelct very less data, approximately 0-1000 data in a second which is very less to the max. 500kS/s what the NI 9201 can collect. the worst is it doesn't react at all if I try to change the samping rate in the FPGA VI (there is a flat secquence in it, which irst frame includes a Loop timer whith a control, to set the rate, and in the second frame there is the reading of the Analog input, and writing it to the FIFO).
We think the problem is that the RT VI does not run on the cRIO (it runs on the PC we think) and many elemnts are lost during the Ethernet communication. My question is how to pace the RT VI on the cRIO, so it can run on it, and not the PC? I think it could be done by building a Realtime Application, but I haven't done anything like this before, as like the rest of this project.
The alap_proba_1_fpga.vi is the FPGA VI, and the alap_jo_1_fpga. vi is the RealTime VI
Thanks for your help!
Regards,
Tschabee91
