10-13-2020 07:20 AM
what happens when we connect a condition to the loop check in SCTLs?
can I check the execution by highlight execution to understand the communication b/w Host & FPGA VIs in simulation mode?
10-13-2020 07:29 AM
@ramya850 wrote: what happens when we connect a condition to the loop check in SCTLs? can I check the execution by highlight execution to understand the communication b/w Host & FPGA VIs in simulation mode?
1. If you connect something to the conditional terminal of an SCTL, the loop will stop executing.
2. You should be able to. See https://zone.ni.com/reference/en-XX/help/371599P-01/lvfpgahelp/running_fpga_vi_on_emulator/
