SIT with FPGA I/O that needs to be conditioned

[Bladhart]

Hello all,

I am new to SIT and need some help. I have been doing the "sine wave" example: http://zone.ni.com/reference/en-XX/help/371504F-01/lvsithowto/sit_h_building_a_model/ , and I have been able to deploy it onto my PXI-8101 with LabView RT. Right now, it can send the sinewave to my AO1 port on the PXI-7833R, and the measured AO1 voltage is -1V to 1V. However, I want to condition the signal to be -10V to 10V (making it 10x bigger) before I send it out the AO1 port in LV.

I also want the inputs (frequency and amplitude) to be controlled by AI0 and AI1, where 1V should correspond to 1rad/sec and 10V should correspond to 10rad/sec.

It is not obvious how I can do that within the given structure in this example (hence, I can't figure out how do it in general). Also, changing the simulink dll isn't an option (because we use the same model for something else).

[Patricia B]

Hello,

You can connect to SIT and be able to change the frequency and amplitude values with property nodes but the output must be a control. You may wan to consider making the control invisible on the front panel so that no one inadvertently changes the value. In order to create the property node, right click the control, click create property node, click value. Wire the output of the FPGA to value. Use a local variable to write the AO to the FPGA. Hope this helps.

Best,