SPI & I2C Driver API

[Scott.Longe]

I'm downloading and installing it now, but I'm afraid that I have the same issue as this user here. Some bug with LabVIEW 2014 and the CLIP IO added to my FPGA. I'll look into upgarding my LabVIEW....

I'll let you know if the drivers fix anything.

Thanks,

Scott

[ericthemantis]

Hi Scott,

I checked out that link. That is correct, this was a bug in LabVIEW 2014 with FlexRIO FAMs. And the post is correct, it was fixed in LabVIEW 2015. I only setup the example with a simulated R Series card, not a FlexRIO, so I didn't see the error. You will need to upgrade LabVIEW to use the Desktop Execution Node with your FlexRIO FAM. The example should run on HW, and it should run simulated, but unfortunately not with the DEN in LV 2014.

Hope that helps,

[Scott.Longe]

Hello Eric,

I was fortunate enough to be able to upgrade to LabVIEW 2016 and fix the DEN error, but I can't seem to configure the DEN to look like yours. My DEN is not showing any I/O's under the available resources settings.   

Do you know what the issue might be here? What does your FPGA.vi look like?

Thanks,

Scott

[ericthemantis]

Hi Scott,

I dug a little further and found that CLIPs for FlexRIO FAMs don't work with the DEN. Sorry I didn't catch that earlier. Otherwise, the I/O would show up in the available resources. 

If you really want to simulate before trying real hw, you could create some FPGA controls and indicators to represent the Master and Slave pins in the FPGA vi to add the same type of simulation functionality. You could implement some Conditional Structures like so -

 Once you are ready to test with real hardware, the controls and indicators you created won't be needed anymore, hense the conditional diagrams. In both the simulation and with real HW it would probably be better to use an FPGA I/O node host side, like so- 

You'd then have another I/O node for the simulated signals to connect up to the feedback nodes. I didn't go through and replace all the FPGA I/O nodes on the FPGA vi, but I think this is the direction that would work moving forward for you.

Hope that helps.

-Eric

[Scott.Longe]

Hi Eric,

I managed to correct all errors in both the host.vi and fpga.vi and create a build specification, but when I try to run the host.vi LabVIEW always crashes. 

Is there any documentation for the NI SPI IP anywhere? Looking at this page I don't see anything. There are some things I am unclear about, like what the Divider control is intended for. Is it a divider for the FPGA clock frequency?

At this point I am not sure how to proceed due to the constant crashing so I've attached my project in hopes that you might be able to catch something I missed or to see if I am implementing something incorrectly.

Thanks,

Scott

[Scott.Longe]

Actually I missed the note on the location of the documentaion for the example:

Additional Documentation:

• After Installation - C:\Program Files (x86)\National Instruments\LabVIEW 2012\user.lib\_NI SPI IP\documentation\NI 5644R Serial Peripheral Interface (SPI) Example.pdf

I'll look through this and see if it helps.

Thanks again,

Scott

[javathi42]

I also have a similar implementation.

The same SPI implementation on NI7961R and its IO adapter module NI6583.

I changed all the things that are required like IO modules and added some more in the FPGA VI like IO Module IO enable all that are required to run in my target and IO module.

The program runs successfully with DIO0(Master -CS), DIO1(Master -CLK), DIO2(Master -MOSI) and DIO3(Master -MISO) and corresponding Slave signal.

In the front panel of the HOST VI what ever I am giving in the Master Write comes in Slave Read and press start. other than that in the SPI Bus Data no changes are reflecting except a few. 

Could you please explain me briefly the working of this implementation so that I could continue my thesis This is troubling me a lot.

Also suggest me some other easy ways of SPI implementation using NI7961R and NI6583 if possible.

Thank you in advance.

Best Regards,

Jagan