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Saving FPGA time + Cannot find "Get Simulated Time VI"

Hi,

 

I am using LABVIEW FPGA to collect some data (500 msec loop timer). I have cRIO 9014, and using FIFO method in FPGA. In addition to saving data in a file (in real time mode), I want to save the TIME that the data is collected.

 

I found this link http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgahost/fpga_get_sim_time/#instance2    which I believe should work for me, but the problem is I cannot find it between my FPGA VIs.

 

any idea how I can use this VI or where I can find it? Should I have to install any additional toolbox?

 

However, If you know any other method to save FPGA time in addition to data, please let me know.

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Hi far,

 

that function you linked to is in a function palette called "Simulation VIs". I don't think you want to simulated those FPGA algorithm…

 

You could create your own timestamp in the FPGA starting at zero when the cRIO powers up (or your RTEXE loads the bitfile). In the RT part you can do some additional math to correlate FPGA time counter with "real" clock…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Thanks for quick reply. could you please explain more about the this timestamp in FPGA and then relating it to  real clock.

 

I am beginner in Labview so I need some more hints or example to use your method

 

 

Thanks again

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Hi far,

 

you could something similar on your cRIO:

check.png

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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GerdW,

 

The code you provided works in real time VI. I am recieiving the data from FPGA buffer. So the time each data is collected in FPGA is imprtant for me, and not the time my real time VI is running. 

 

To be honest, I set the loop timer in FPGA to 500 msec which is 2000 hz, so my interval between each data should 0.0005 sec. by saving time that each sample is colleceted in FPGA, I want to make sure may sampling frequency is actually 2000Hz (maybe that sounds like stupid, but I am newbie and I don't trust my results)

 

So, what would be the best way to collect the time in FPGA?

 

 

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Hi far,

 

500ms means 2Hz for me, but not 2kHz…

 

To "collect" time on FPGA you could use the "Tick Count" function found in the "Time" FPGA function palette. It works the same way as TickCount on RT target or Windows: you get a relative timestamp and you need to add the "real clock" to get an absolute timestamp (as shown above)…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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