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Simple question about analog signal muxing w/ case structure

Hello!

 

I am trying to generate a signal as follows:

 

-if the clock signal (square wave in vi) is 1, then select the sine wave

-if the clock signal (square wave in vi) is 0, then select the DC

 

So, I've designed the vi like this.

 

-  vi for the "False" case (for DC)

TSMC018_0-1646721459372.png

 

 

-  vi for the "True" case (for sine wave)

TSMC018_1-1646721705132.png

 

And the result is as follows.

TSMC018_2-1646721737823.png

 

The output seems like the case structure is always on "False".

 

Is there any way to generate a desired signal?

 

 

 

 

 

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Hi TSMC,

 

what would happen when you get rid of all those ExpressVIs and their DDT wires and use simple plain LabVIEW functions?

 

Btw. you know we cannot run/edit/debug images with LabVIEW. When you have problems with your code then you should attach your code!

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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