Single Cycle Time Loop

[loghmani]

Hi

I wrote two FPGA programs one with SCTL and one without SCTL. Both of these programs are the same(except in using SCTL). The result is strange for me. The first Program(with SCTL) uses very low of resources:

(Total Slices : 4.5% , Slice Registers: 1.2% , Slice LUTs :2.6% , DSP48s: 1.7%)

While the resources which the other program uses are very higher than the first one :

(Total Slices : 38% , Slice Registers: 18.2% , Slice LUTs :26.5% , DSP48s: 27.6%)

I want to know, is this huge difference, normal? 

Thanks

[ToeCutter]

Yes this does seem strange. Can you show us your code?

[loghmani]

I have attached both of FPGA VIs. The hardware is sbRIO-9626.

[altenbach]

Does the code with the SCTL actually work? It seems to me that most code is unreachable because the first SCTL never completes. All it does is repeat the same operation, and since it never produces any output, everything is probably optimized away, leaving you with basically an empty diagram. 😄 

Try wiring a TRUE to the termination conditions of the SCTLs and see what happens.  (see also here)

("Single cycle" does not mean that it executes only once. It means that the code in it needs to complete in a single FPGA tick so the loop can spin at the FPGA clock rate.)

[crossrulz]

Yes, the SCTL will cause your usage to go down.  The reason is that the SCTL causes LabVIEW to remove a bunch of buffers inside of the loop.  It can do this since all of the code inside of the loop will execute in a single FPGA clock cycle.

Your code with the SCTL will not work as is.  You need to wire in a TRUE to the termination for all of your SCTL.  Also, you have a rotate array inside of a SCTL, which won't work.

Quickly looking at your code, you should be able to use just a singe SCTL to encompass all of your code (instead of your big while loop).  You just need to work around those Rotate 1D Arrays.  That is simple enough by keeping track of which element you want to replace.  So instead of rotating the array, you just circularly replace a different element.  We might also have to work around the FOR loops that add up your fixed point numbers.  I have other thoughts for that, but not formulized enough right now to put down.

[loghmani]

Thank you. I did what you said. In this time, the compiler give errors becuase of lack of LUT blocks whereas I expected that this VI uses lower resources comparing to the other VI without SCTL, because of using SCTL .

I have attached the VI and XilinxLog.

[loghmani]

1) Can I do the calculation in the Host VI under RT target and only use the FPGA for reading input and writing on the output port?

2) Does the RT target (sbRIO-9626) support my calculation?

3) Are there any issues of lack of resource regarding to it?

[altenbach]

Earlier you said that the version without SCTL works, why don't you use that?

Your diagram contains a lot of garbage, for example why is there an empty extra loop? What's with all these to I32 conversions everywhere? As was suggested, why don't you eliminate the array rotations and keep track of the index instead?

[loghmani]

I omitted the blank loop. The I32 conversion is becuse of below tutorial of NI (I use I8 constant and convert it to I32 in the input of initialze array)

Maybe is it optimized to use a I32 constant and connect it to the initialize array?

The rotaion is because of adaptive filter algorithm. In every execution of the loop, the last element in the array must omit and one new data goes to the first element (like a FIFO). I don't understand keeping track of the index. Can I do these FIFO liked operation with keeping track of the index?

What about For loops, is there any optimized way to replace them?

Thanks

[altenbach]

I don't think these coercions are a problem that you need to solve explicitely.

You have an array of 20 elements that you constantly rotate while replacing the first element. For each rotation, all elements need to be moved around. You could easily keep the array elements in place and instead maintain an index in a shift register that keeps strack of the position of the oldest element so you know which one to replace next.