I see a number of problems here, but I don't think you'll get to 40khz even if you fix all of them.
First, you have Wait until Next Ms Multiple inside the timed loop, with the value set to 1 ms. So that loop won't ever execute faster than 1khz. There's no need for a separate wait inside a Timed Loop - use the loop timing. In addition you have the DMA FIFO read, which will limit the timing to whichever is slower - the DMA read, or the 1ms wait. On the other hand, if you didn't have something else inside the loop limiting the loop rate, the 1mhz cycle time would probably consume all the CPU time and network communication would fail. My recommendation is that you use only one timing mechanism in the loop.
Second, you should not configure the DMA FIFO depth to be so small; it will likely lead to the DMA filling and losing data. Try removing the FIFO configure and let it use the default depth, unless you have some specific reason to change it. The FPGA will normally run much faster than the host, so the FPGA will write small amounts of data to the FIFO frequently and the host reads much larger blocks at a slower rate. In your case you're trying to keep them matched, implying that the host and FPGA run at the same loop rate, which is unlikely to work well. The host probably cannot process samples as fast as the FPGA can read them, if you're trying to process each value individually.
Finally, if you really want to maximize the sampling rate and transfer to the host, then you should read one input while you write the previous one to the FIFO, instead of reading all 8 inputs and then writing them individually to the FIFO. In your current situation there is no sampling while you write to the FIFO, and no transfers to the FIFO while you're sampling.
