Synchronize two DMA FIFO read operations

[SunJab]

Hi,

I am using two DMA FIFOs to transfer data from host to the FPGA target... Is there any way to synchronize the two DMA FIFO read operation in a single cycle timed loop?

thanks

[Ben_S]

Sandee,

What do you mean by "Synchronize two DMA FIFO read operation in a single cycle timed loop". By defintion, a SCTL (Single Cycle Timed Loop) will execute in 1 clock cycle so anything in it will happen at the same time.

[SunJab]

I am transfering I and Q data from host to the FPGA using two DMA FIFOs and reading them in the FPGA vi inside a single cycle timed loop. but I am not able to read I sample with its corresponding Q sample. i.e IQ samples don't come at the same instant (I0 doesn't come with Q0, I1 doesn't come with Q1 and so on...).

Message Edited by Sandee on 04-26-2010 11:50 PM

[Ben_S]

Sandee,

Can you ensure that you are writing the data synchronsly? If the data isn't being written at the same time in the Host you could see this issue. If your FPGA is simply reading from the FIFO as fast as it can, it may be able to pull data so much faster than the RT that between writing the data for I and Q it is able to read I then Q. 

I would suggest using IRQ's to do some sort of handshaking to ensure data had been put into the FIFO before you read it in the FPGA.

[GrantS]

Hi,

   I think I may be having a similar problem to the OP here, except I need my two FIFO writes to the FPGA to be synchronized. What kind of programming would I need to accomplish this?

Thanks for the help,

Grant

[siruseri]

Can I know,how to synchronize the FIFO data transmission(read&write)  between the FIFOs

regards,

Dinesh Prasath