TEDS error number 65006 when using synchronized data

[rstebner]

I'll apologize ahead of time because this is going to be long.  However, I'd love any help I can get and I think this might help a few others out there.

I have a cRIO-9102 with two NI 9237 modules.  For the first 9237 module I set the Master Timebase Source to the Onboard Clock, and exported the clock.  For the second module I set the Master Timebase Source to the exported clock from the first module.  In my FPGA code I have a FPGA I/O Node that reads analog data from all 8 channels on the two separate 9237 modules.  When I want to acquire data I set the Start to True for both modules.  When I want to read the TEDS information I set the Stop to True for both modules.  I can successfully read from the first module (the one that uses it's own onboard clock).  However, every time I try to read from the second module I get error number 65006:

CompactRIO:  (Hex 0xFDEE) Communication with the module timed out. The module is busy performing another action or LabVIEW is unable to communicate with the module.

I even tried modifying the NI 9237 Getting Started example to have two modules with synchronized data, and got the same 65006 error.  The error seems to indicate that the acquisition mode wasn't stopped, but I am setting Stop to True for both modules.  So I've been going through a lot of trial and error trying to find a solution (which is painstakingly slow when you have to repeatedly recompile the FPGA code), and a lot of reading through the help files and examples.

The "Accessing TEDS Information from the NI 9237" help page has a note that says:

"The FPGA VI must have an FPGA I/O Node or an FPGA I/O Property Node that communicates with the NI 9237. If it does not, the LabVIEW FPGA Compile Server optimizes the VI when you compile it, and the host VI cannot communicate with the NI 9237."

When I first read that I thought that could have been the problem, but my FPGA code has a property node for both modules to set the data rate.  Also, I have FPGA I/O Nodes for both modules to set the Start and Stop values (plus another FPGA I/O Node that combines reading the analog data from both modules).

I finally found a workaround.  First, I configure both 9237 modules to use their own onboard clock.  Then I use two separate FPGA I/O Nodes (since there is a requirement that a single I/O node can only read from multiple modules if they are synchronized) to read the analog data from the two separate modules.  Now when I set Stop to True for both modules and read the TEDS data everything works as expected.

If there is anyone out there that gets the 65006 error message try changing your FPGA code as I mentioned.  Otherwise, does anyone know how to fix this issue while still having synchronized data (master/slave timebase configuration)?

[Ipshita_C]

Hi rstebner,

Can you please post a screenshot of your error and your FPGA code? Thanks!

Ipshita C.

[rstebner]

Dear Ipshita,

Thank you for the response.  To make things easier I'll attach my modified version of the "NI 9237 Getting Started" code.  I took the "NI 9237 Getting Started" example and made only these changes:

- changed the backplane to match mine

- updated the modules and their corresponding slots

- based the second 9237 module (slot 3) timebase on the onboard clock of the first 9237 module (slot 2)

- added a control to select between slot 2 and slot 3

- wired the data rate to both modules in the FPGA code

- wired the Start and Stop for both modules

- the FPGA I/O node is also saved as acquiring data from the second module, but I originally had it acquiring from the first module (I just wanted to make sure that didn't make a difference)

This should be easier for debugging purposes than giving my full application.  I've attached two pictures:

Success.jpg is a screenshot when I read from the first module (with the onboard clock)

Failure.jpg is a screenshot of the error I get when I attempt to read from the second module

Thank you for your help.

~Russ

[Ipshita_C]

Hi rstebner,

Please have a look at this tutorial that gives you more information on synchronizing delta-sigma modules with the compactRIO. I think in your case, there is a delay in the time that the first one's timebase updates the second one and this delay has not been incorporated in your code. It would also be a good idea to know what structure you are using to implement the master-slave architecture. 

Ipshita C.

[rstebner]

Dear Ipshita,

Thanks for the response, and I hadn't seen that tutorial before.  Unfortunately, Figure 1, Figure 2, and the attached image in that tutorial are not loading for me.  Any chance you can fix the problems with the tutorial?

So what exactly does sharing the master timebase do with the 9237 modules if it doesn't actually synchronize the data?  Also, after issuing the start and stop commands I've tried adding delays before continuing and that didn't seem to help.  Maybe the delay wasn't long enough.

Finally, what exactly do you mean by this:

>> t would also be a good idea to know what structure you are using to implement the master-slave architecture. 

How does the master-slave apply to that 9237 Getting started example?

Thanks.

~Russ

[Robbob]

Rstebner,

Are you stopping both modules simultaneously?  Since the slave module is dependent on the master's timebase, maybe you should stop the slave first and then the master.

A good way to test this would be to stop JUST the slave, and see if you can read the TEDS data from that module. I would test this myself, but I have no TEDS sensors around at the moment.

Let me know how it works out, and I'll see if I can get a hold of some hardware in the meantime.

[rstebner]

Dear Rob,

I am stopping the modules simultaneously because that is what I saw in the examples and what was recommended in the help pages.  However, I will try stopping the slave first as you suggested.  I don't have access to the hardware right now, so I will try this on Monday and report back.  Thanks for the suggestion.

~Russ

[rstebner]

Dear Rob,

I recompiled the FPGA code to have the slave stop before the master.  I even added a delay (wait for 1000 ticks) between stopping the two modules, and it didn't seem to fix the problem.  I still get error 65006 when trying to read from the slave module.

For testing purposes if you don't have access to a TEDS chip you can still recreate the error I receive.  I unplugged all 8 of my TEDS sensors.  The master module returns with the correct error number 65007 for a missing TEDS chip, but the slave module returns 65006.

~Russ

[Ipshita_C]

Hi Russ,

To verify, you are getting the same error even when you have unplugged all of the TEDS sensors. Just in order to isolate this as something to do with the modules have you observed if you get any errors when you use the onboard clock with both the modules?

Ipshita C.

[rstebner]

Ipshita,

To reiterate, here are the the results I get:

1.  Synchronized data (9237 module 2 uses the exported onboard clock from module 1)

Module 1 can read a TEDS chip without an error.

Any channel on module 1 without a TEDS chip properly returns error 65007.

Module 2 always returns error 65006 regardless of whether or not a TEDS chip is present.

2.  Non-synchronized data (each module uses it's own onboard clock)

Module 1 and Module 2 can read a TEDS chip without an error.

Any channel on module 1 or 2 without a TEDS chip properly returns error 65007.

~Russ