Target relative user defined variable broken in FPGA context

[Omar_Mussa]

If I use "target relative" reference mode for a UDV in an FPGA VI, the VI becomes broken with the error "The variable is not in the project. Either add the variable container to the project, or link to a different variable."  However, if I right click on the UDV in the VI and select 'Show in project' its clear that the UDV can be found.  I want to use the same FPGA VI with the same UDVs on several different cRIO targets.  I tried making the variables relative because  if I do this in absolute mode I get a different error ("The variable project item is in a location that the FPGA does not support - absolute mode generating an error makes sense to me).   I tried to open the attached example project in both LabVIEW 2014 and 2014 SP1 and both versions have the same issue.  Is there something I need to do differently or is this a LabVIEW bug?

[muffin.vi]

Omar_Mussa,

I'm a little confused. UDVs are referenced at the chassis level. How would you refer to the same UDVs from multiple targets without being on different chassis?

[Omar_Mussa]

Hi Kyle,

Here's what I want - I want to have an FPGA VI that can be moved to a different chassis and reference the UDV on my new chassis without breaking.  I assumed 'Target Relative' meant that the UDV referenced in the FPGA target would find the relative path to the UDV on my chassis so that I could reuse my FPGA VI on multiple chassis without having broken code but my FPGA VI broke.

In the screenshot below - I want to have "FPGA Main.vi" be able to access the UDV "MyVar" on the chassis that the FPGA is located.

Here is the error LabVIEW reports:

These errors seem to imply that the UDV variables are not working in relative mode.  It looks to me like the relative path ('.\') is not being resolved by the editor and/or compiler (which seems to me to be a bug unless I am misunderstanding something still).  I re-attached the source project for my new use case.

[muffin.vi]

Omar_Mussa,

Thanks for the additional info. I'm going to check in with some of the engineers in R&D to see if this is expected behavior or not. Give me a few days to check things with them, and I'll get back to you. 

[muffin.vi]

Omar_Mussa,

It looks like this is expected behavior--more or less. The option to select target-relative is a carryover from RT that isn't really relevant with how UDVs are handled in FPGAs. Basically, that option shouldn't exist and you are very correct in recognizing that. I'll talk to R&D and see if we can make that fix in future versions. 

[Omar_Mussa]

Ok, that makes sense I guess.  Is there a way for me to accomplish my original goal - i.e. make my code transferrable between multiple cRIOs without having to create custom FPGA VIs on each RIO to link to the UDVs on the chassis where the FPGA exists?  I really want to reuse my code between muliple chassis.

[muffin.vi]

Omar_Mussa,

I don't believe you'll need to make a custom FPGA VI. You will need to create a new UDV library for each chassis, so it would just be a matter of linking to those UDVs.