Target-scoped FIFO in case structure won't excecute

[fuaran]

Hello,

I am trying to count the time in ticks between rising edges on two digital channels. Therefore I use a myRIO and LabVIEW 2013 SP1 on a Windows 7 PC.

As you can see in the attached picture, I use a target-scoped FIFO to pass the number of ticks between two events from SCTLs to a while-loop, where I want to send them via DMA to the RT host.

I chose this design to limit the number of DMA cannels and to increase the clock of the SCTLs (allows better precision in time). The number of ticks is determined via the built-in DSP 32bit-counter.

However, when I run the VI no data is written to the target-scoped FIFOs. "Number of Elements to write" is always 127 (128 requestet), "Number of Elements to read" is always zero. "ch0 post" indicates that the "true" state of the case structure is actually entered.

Edit: All the indicators were added for debugging purposes. The simulation on the PC indicates no errors whatsoever, but I realized that no data is written to the RT host when in actual use.

I checked out the cRIO programmers guide and the High Performace FPGA Developers Guide and fail to see where I went wrong. Yet it won't work.

I'd be happy if someone could help me fix this problem!

[dan_u · Accepted solution]

In the lower while loop what do you do if one of the FIFO read timed out (non-zero cases in the case structure)?

If you set the boolean to False in the other cases (1..3) then you will only send something to the host when both FIFOs received data in the same loop iteration.

If it receives a tick count on one FIFO in one iteration and a tick count on the other FIFO in the next iteration timed out will never be zero.

Maybe to debug you could store the 'tick count ch0 fifo' value in a shift register and update it only when the delta_c_ch0 FIFO did not time out. Then you can see if this value is ever different from zero.

[dan_u]

Sorry for double post, hit 'Post' 2 times.

[fuaran]

The cases in the lower while loop set the value of the inactive channel to zero. If both are inactive a false constant is forwarded, so tht the FIFO is not excecuted. I guess that's overdoing it a bit, but I didn't want to leave it to chance whether the default "0" is set or not.

Your advice was helpful, thanks! I now know that the FPGA VI is working as it should and have to reexamine the RT part. Somehow I only read zeros (nothing, respectively) from the delta_c_rt FIFO...