Time dependent programming in FPGA

[adam_f]

I think my problem is simple, but I need some help...

In an FPGA VI, I acquire an input and compare it to a control (if the input is greater than the control, the code contiues with a fault response).

What I want to do is add a time condition.

I only want to continue with the fault reponse if the input is greater than the control and it has been greater than the control for x amount of time.

What is a good way to do this?

Thank you. 

[Hooovahh]

FPGA has a Timing palette with Wait and Tick Count.  These can both be configured to use Ticks, micro seconds, or milliseconds.  Say you want to know when some amount of time has elapsed.  You can take your Ticks at the start of some condition, then in a while loop subtract from the current Ticks, the Ticks that you took before the while loop.  The number of Ticks in a second will change as your clock rate changes, so it maybe a good idea to use micro seconds or milliseconds if you don't want to worry about having to change code based on a new clock.

[T-REX$ · Accepted solution]

I adapted the below code from the 2013 Watchdog example. Instead of waiting for the watchdog to get whacked, it waits for the IO to go above the setpoint. This one is timed in milliseconds, but you could use ticks for better resolution, just make sure to keep your loop rate in mind.

You can check out the example for documentation on how the code works if you need it 🙂

[PatrickR]

You could use a single cycle timed loop, with a counter and count ticks.

[adam_f]

Very helpful.

Thanks!