Timing Problem with 7830R analog output

[chrissyPu]

Hi,

im using a 7830R for my diploma thesis and want to give out a Sine function with variable Amplitude with up to 1 kHz from a LUT with 1024 entries. Using the maximum output rate of the analogue channels of 1 MS/s this should work roughly up to 975 Hz (1MS / 1024 S = Number of Periods per Second).

I implemented this with the LUT ExpressVI which I initialize with a 1024 Sample Sine Function at full scale (16bit). The output value is cast to a 32bit Integer and multiplied with an 16bit Amplitude factor, afterwards scaled with 2^-16 to archieve a scaled output with a maximum of 16bit and with the least possible rounding errors due to the Integer multiplications. I put the whole scaling part in a  Single-Cycle-Execution loop. All of this is placed in a For-Loop with 1024 iterations to give out a whole sine period. This for loop is also placed in a second for loop to have control about the number of periods given out. The output frequency is controlled by the Value of the Tick Counter.

To make understanding easier, the picture of my code is attached (I don't have access to a server to include it here right now).

Now to my problem: The code works fine but I can't get any frequency about 800 Hz out of the FPGA. Does anybody have an Idea, why this happens?

The code also has some other elements, but these are not active while using the sine output part.

Thanks for your help,

Christian

[ThSa]

Christian,

generally your computation is correct but in your case you've forgotten to consider some other important parts in your FPGA app.
You can benchmark easily the execution time of the inner and outer for loop. By doing so, you can compute the possible max. frequency.

Thanks,
ThSa

[chrissyPu]

Hi ThSa,

you're right, I could benchmark the loops, but that wouldn't take me any nearer to use the full 1MSa output of the card. What other important parts of my app could influence the execution time of my loops? Perhaps you've got an idea based on your work with FPGA apps.

thanks,

ch

[ThSa]

Christian,

use pipelining (see FPGA online tutorial) instead of a sequential dataflow.
Furthermore, instead of using nested for loops (a for loop does have an overhead of 2 ticks), either use a while loop or only one for loop with your own remainder functionality.

ThSa

[chrissyPu]

Hi,

thanks for the advice with the nested loops and the pipelining. With only one loop and two pipelines (the parallel elements are therefore reading the LUT, calculate the gain and giving out the signal) I get a frequency of 930 Hz.

Since you're from NI, can you tell me how long the writing to analog out part takes the FPGA? And is there any better solution for getting the rest of a division than using a bitwise AND? (I checked, this works for all divisors that are a power of 2 and takes  less FPGA resources than a Q/R-Block).

Thanks for your help,

Christian

[ThSa]

Christian,

reading/writing from/to an analog input/output takes either exactly the conversion time you have set or exactly the max. acquisition rate. In your case it is to much to split the "LUT;computation;AO" in three clumps, it is enough to have two independent flows. Because of the absolutely parallel execution on FPGA the loop iteration time is dependend from the longest line in the loop. In your case, this is definitely the AO operation. The Q/R block takes about 20ticks for processing and the slice wastage is amazing in comparison to an AND or shift operation.

The way to use a bitwise AND is not really working, instead of this use the multiplication and substraction function in a SCTL.

ThSa

[chrissyPu]

Hi,

I hope I'm not annoying you, but what do you mean with:

>The way to use a bitwise AND is not really working, instead of this use the multiplication and substraction function in a SCTL.

From the mathematical view, a bitwise AND-Operation of a number with - for example - 1023 gives the remainder of the division by 1024 and it works fine with my code (also tested with LUT-sizes up to 8192). Why do you think this is not working? Although my class about logic gate design is a couple years away, I recall some AND-gates should be more efficient than operations with carry bits like multiplication and subtraction...

Since I actual expect some knowledge increase from writing my diploma thesis I'd appreciate some more "Why to do something in this way" in addition to the really helpful "Do it this way".  This is no offence, but I really think this would help me to understand the FPGA-System further and perhaps help me to solve problems by my own... 😉 Thanks,

Christian

[ThSa]

In your specific case bitwise AND is working of course, but it's not the common solution.
Multiplication and substraction needs about 2.5 times more logic on FPGA than the AND function (depending on the datatype) but it is usefull for "all" cases.

ThSa