Timing a while loop for a specific frequency on cRIO

[Vedi]

Hey

I'm working on creating a simulator where I use a cRIO-9012 with a 9265 AO. The data to be sent are read from file then continuously accessed point by point from the read array. The problem is that the loop currently operates at 31KHz, but I need it to be 25kHz.

Any reply will be appreciated.

Vedi 

[DBerry]

Have you specified the loop rate using a timed loop?  What does your VI look like?

Dan

[Vedi]

Hey, I have not tried a timed loop yet. I tried to use a while loop with wait ms and ticks, but it slowed the process to much from 31kHz to 13kHz.

The VI is attached, never mind all the mathmatic operations that seem meaninglesss inside the loop. I just created them as a way of slowing the loop 🙂 

[ninlmartijn]

Hello Verdi,

thank you so much for your forum post.

The timing from your analog output should be arranged by the FPGA VI; you can use a loop here, and with the most accurate timing you are able to update the analog outputs.

Just a quick thought;

With the RT VI you should open the files, do the mathematics and write those in a DMA FIFO. Please have a look at the KB; you need the other way around; host to target DMA.

In the FPGA VI you can read the FIFO and send the values to the analog output on the hardware timing of the FPGA clock (most accurate). Now you can write quite fast the values tot the FIFO in the RT VI (write at once or with blocks) and read those out at the required clock rate in the FPGA VI.

I hope this will bring you further, please don't hesitate to post if you have any further questions.

Best regards,

[Vedi]

Thank you for the reply.

If I understand your post correct, you think I should send the data to the FPGA, use a FIFO and let the FPGA send the AO?

[Vedi]

How can i wirte a FIFO on the cRIO, can't seem to find that option. I can only read on the cRIO and write on the FPGA.

[ninlmartijn]

Dear Verdi,

First of all you create a host to target fifo (please see attachment). In the FPGA VI you can drag and drop the fifo you created in your project. In the host VI you are able to use the FPGA refrence (the same you used to read / write the controls from your FPGA front panel) and place a Invoke method from the FPGA functions palette. Here you should be able to write this fifo. 

Please let me konw if you have any further questions,

Best regards,