Timing constraint: COMP "d<23>" OFFSET = OUT 15.3 ns AFTER COMP "MiteClk";

[Idratherberacing]

What if I offloaded some of the functions into another SCTL that runs on a different clock?  This could be programmed somewhere else on the chip and as long as I had a way to designate which SCTL was "in charge" of DIO pins, I think it might work.  It would reduce the amount of logic gates to be processed by the first SCTL which should allow the DMA FIFO's to compile if I'm understanding things correctly...  Is there a way to access the DIO pins in a way similar to a local variable??

[Idratherberacing]

I just had another idea...  what if I simply made two FPGA VI's??  I could have one run all of the case structures and signal manipulations except for the one labeled "command reception self tests" and then I could just burn the bitfile to the FPGA during testing... Is there any way I can save the bitfiles for each VI after they have been compiled once so they transfer to the FPGA quickly??

I really think that's my best shot since pretty much every structure in the current FPGA VI is time critical...

[Ruhmann]

OK, so you're saying that you don't need your entire application running at the same time?  I think a lot of customers split up their application, so this isn't a bad idea.  How quickly do you need to switch?  Once you have both VIs compiled, closing a reference to one VI and opening the reference to a new VI (which includes the download of the bitfile) ussually takes about a second and I would be shocked if it took more than 5 seconds.

I'm not sure if you know this, but the bitfiles are stored on your computer in a folder called FPGA Bitfiles that should be in the same folder as your project.  You can link the FPGA Interface open nodes directly to these bitfiles so that if you accidentally change your FPGA VI, LabVIEW won't complain and tell you to recompile the VI.

[Idratherberacing]

Wow, one second is perfect.  That's a lot faster than I was expecting...  I think I will pursue that option.  Thanks!

[Idratherberacing]

So I got it to compile by taking out a lot of the extraneous functions.  However, now, the FIFO does not seem to receive any data from the FPGA... Another thing I noticed is that one of the Invoke Method nodes I'm using doesn't appear to be transferring to the FPGA to manipulate a case structure...  I am going to post the host VI, the FPGA VI, and the subVI that runs the PWM to see what you guys think... I've been staring at this too long and need to take a break for a bit.  Thanks for the help and any tips & tricks you guys might have.