Timing violation error when FIFO is used

[Prashant_dsp]

Hi everyone,

I use a NI PCI 7833R board to create a control application using adaptive filters. I have optimized parts of my algorithm using single cycle timed loops so that they all work at 40 MHz. To communicate the result of the application to the host, I use a FIFO of length 1024 (target to host). I copy the results from memory location to FIFO using single cycle timed loop. But when I compile, I get a timing violation error that I overshot 25 ns cycle time by about 3 ns. I do not get this error, if the FIFO is not present in the VI. The transfer from memory to FIFO happens after the algorithm has finished. So why is the FIFO affecting the timing of the algorithm?

I also use interrupts (wait on interrupt) to interact with the host. I observed that if the interrupts are not present or wait on interrupt is set to false, the entire code can execute at a faster clock rate (maximum clock rate from the compile report). However, when wait on interrupt is set to true, the maximum clock rate at which the code executes reduces. Why is this so?

Regards,

Prashant

[Gregor Cerne]

Hello,

In single cycle loop all of the function execute in one tick of the clock. The problem arise when the functions inside single cycle loop need more time to execute than the time allowed from set clock rate - in your case 25ns. In your case writing to FIFO need a little bit more time to execute, that is why you get an timing violation error with using it.

I suggest to use pipelining

[Gregor Cerne]

I apologize for short post - I am experiencing some technical problems.

In single cycle loop all of the function execute in one tick of the clock. The problem arise when the functions inside single cycle loop need more time to execute than the time allowed from set clock rate - in your case 25ns. In your case writing to FIFO need a little bit more time to execute, that is why you get an timing violation error with using it. It is the same with interrupts, with difference that interrupts consumes less time than writing into a FIFO, that is why you don't get an error but only experience decrease of maximum available clock rate.

I suggest to use technique called pipelining - with it you can improve clock rate of execution with cost of delay of few ticks. How to implement it and further information about this technique is described in provided link:

http://zone.ni.com/reference/en-XX/help/371599F-01/lvfpgaconcepts/fpga_pipelining/

If you have further question regarding your problem fell free to ask.

Regards,

Gregor Cerne

[Dragis]

Gregor's approach should work for you, but I wanted to mention that reducing the timed loop clock that shuffled the data to the host to 20 MHz may also be an easy solution.

[Prashant_dsp]

Thanks Gregor and Dragis, I will check if pipelining helps. I cannot reduce the clock rate below 40 MHz. I would be glad if to work at a higher clock rate, but I cannot reduce the clock rate any further.

Thanks,

Prashant