05-24-2019 02:42 AM
Hi all
I'm want to use UDP to stream torque data from an HBM TIM-EC module to my cRIO 9047.
I can stream data directly from the HBM module to my host pc using the attached VI.
I want to get this up running on my cRIO (Eventually on the FPGA chip), since I need to sample with at least 20 kHz.
The HBM module is capable of sending data with 38 kHz.
The challenge is to have no loss of data during the data acquisition. Any suggestions how to implement this?
05-24-2019 05:57 AM
Hi,
when you talk about UDP, it is not possible to ensure no loss of data.
UDP is an unreliable, light weight protocol with no handshaking dialogues.
Regards
Kaba
05-27-2019 02:45 AM - edited 05-27-2019 02:46 AM
Hey mkstech,
As far as I understand the promo website of the HBM TIM-EC, it is an EtherCAT device. Would that be an option for you? EtherCAT drivers for cRIO exists.
I could not find information on UDP support, however if your VI works that it does obviously support UDP as well.
As Kaba already wrote, UDP itself does not have any handshaking, so you cannot guarantee "no loss" when using UDP. (Side-note: Implementing handshaking on a higher layer like in QUIC protocol is possible, however coding inside the TIM-EC won't be possible).
Regarding UDP on cRIO: It works using RT Linux on the Intel Atom CPU. Inside FPGA however, it won't work. The Ethernet ports are connected to the Intel CPU, which itself interfaces the FPGA. So there is no direct connection between Ethernet and FPGA.
Also, I believe you don't want this. As you wrote "on the FPGA chip, [...] since I need to sample with at least 20 kHz" I believe there is misunderstanding. The FPGA is not faster than the CPU, it is just more deterministic. The normal CPU should be able to handle 20kHz sampling rate (and some analysis) without any problem.
05-27-2019 05:05 AM
Hey Ikaiser
Thanks for the reply
Using EtherCAT to sample data from the HBM module was my first approach, but since this didn't work I tried UDP.
I did follow this turtorial regarding etherCAT on cRIO:
https://knowledge.ni.com/KnowledgeArticleDetails?id=kA00Z000000P9CqSAK&l=da-DK
As another part of the project I have to sample encoder values from the SEA 9521 module.
This module is right now implemented in the FPGA part. Here I must sample from 4 encoder read heads with 20 kHz.
The plan was to do the above and then sample the TIM-EC via the RT-controller and send the torque date to the FPGA via one FIFO.
A big challenge for me is to ensure to the client that the data from HBM-module and SEA 9521 moduel is sampled at the exatly the same time.
But if you say that it is possible to do sampling with 20 kHz with the RT controller I could implement the SEA to the RT-controller instead of using the FPGA??
Do you know if there is any guides on how to get data from EtherCAT slaves into labview? See my approach in the attached pictures.
05-27-2019 07:38 AM
A big challenge for me is to ensure to the client that the data from HBM-module and SEA 9521 moduel is sampled at the exatly the same time.
I'd say this is the real challenge of your project. What do you mean by "exactly the same time"? How much difference is allowed? Does the HBM TIM-EC include timestamps within its data? If so, what clock source does it use? If not, and you send through UDP/TCP, you'll have an unknown amount of network latency. With EtherCAT, you'll at least have a guaranteed maximum latency.
Do you know if there is any guides on how to get data from EtherCAT slaves into labview?
Generally the approach you screenshot'ed is correct. But screenshots show only a little cutout of the whole story.
In the project manager, did it find the TIM EC automatically? Or did you trick it into the project somehow? If not it looks like the "NI-Industrial Communications for EtherCAT" driver and your hardware connections are set up correctly (including setting the cRIO's second Ethernet to EtherCAT). How have you connected the EtherCAT devices?
But if you say that it is possible to do sampling with 20 kHz with the RT controller I could implement the SEA to the RT-controller instead of using the FPGA??
Well, I don't say it's to fulfill all your requirements, I just say it is possible to process a data stream of 20k samples per second inside the RT part. I did not know about the SEA module before, so depending on what you want to do there, you might still need custom FPGA code.
05-28-2019 01:59 AM
The TIM-EC modules was found automatically by labview. I think the setup was done correctly 🙂
I have some FPGA code for the SEA encoder module, since it is stated in the software manual:
"SEA 9521 is not supported in systems without a FPGA programmable backplane like CompactDAQ."
The SEA encoder data is sent to the RT controller via an FIFO and thereby the data is written a spreadsheet.