The timeout function is supposed to be there when the system is idle, it is for example helpful when the VI is started and the FPGA reports that it still has data to send.
So I don't need the timeout during measurements and it is not imperative for the rest. I could disable it alltogether or maybe just disable it during the measurements using a refnum.
That should eliminate the race condition since the FPGA will never send data without first receiving a request from LV.
