Usage of fixpoint division inside SCTL?

[Tim.P]

Hi,

I use the fixpoint math library inside my fpga for division inside a SCTL. If I configure the division node for SCTL, I get a new input ("valid input") and two new outputs ("valid output" and "ready for input"). I'm not sure about the usage of these inputs. Can someone enlighten me?

Thanks for any help in advance.

Tim

[Christian Mergl]

Hi Tim,

The LV Help says:

input valid	Specifies whether the next data point has arrived for processing. Wire the output valid output of an upstream node to this input to transfer data from the upstream node to this node. To display this handshaking terminal, select the Inside single-cycle Timed Loop option in the configuration dialog box.
ready for output	Specifies whether downstream nodes are ready for this node to return a new value. The default is TRUE. Use a Feedback Node to wire the ready for input output of a downstream node to this input of the current node. Note  If this terminal is FALSE during a given cycle, the output valid terminal returns FALSE during that cycle. To display this terminal, select the Inside single-cycle Timed Loop option in the configuration dialog box.

output valid	Returns TRUE if this node has computed a result that downstream nodes can use. Use this terminal for handshaking with other FPGA VIs and functions. To display this terminal, select the Inside single-cycle Timed Loop option in the configuration dialog box.
ready for input	Returns TRUE if this node is ready to accept new input data. Use a Feedback Node to wire this output to the ready for output input of an upstream node. Note  If this terminal returns FALSE during a given cycle, LabVIEW discards any data that other nodes send to this node during the following cycle. LabVIEW discards this data even if the input valid terminal is TRUE during the following cycle. To display this terminal, select the Inside single-cycle Timed Loop option in the configuration dialog box.