Using Host memory buffers for data transfer between Host (RT) and target (FPGA)

[parsec43]

I am a little confused by the usage of host memory buffers for host to target data transfer. When attempting to place host memory buffer methods on the FPGA, I get errors suggesting that I must use (all three) Write, Request and Retrieve data methods. 

Simplistically I would have assumed that I could just request and retrieve data methods on the FPGA, and use the Open host memory buffer VI on the RT to create an EDVR, and then use an in place element structure to write data from the RT host as the Host memory buffer white paper suggests.

https://www.ni.com/en/support/documentation/supplemental/17/host-memory-buffer-overview.html

Am I missing something here. Is there an example available that demonstrates a working FPGA and RT implementation of host memory buffers for fast data transfer from the host to target?

[Intaris]

A DMA transfer buffer is like a FIFO, a QUEUE, not a single-address memory.

This applies to both directions.

A DMA on FPGA will have either Write (target-to-host) OR Read (host-to-target), not both. Are you sure you instantiated a DMA channel and not a normal FIFO?

[parsec43]

My understanding is that it is neither a DMA or a FIFO.

It is DRAM memory, configured by right clicking in the project (within the FPGA) and selecting new, Memory and then choosing DRAM under implementation. The DRAM bank dropdown then appears which has Host Memory Buffer selected. This is purported to be a new method for Host to Target communication, and my understanding is that it is NOT like a FIFO or queue.

[Intaris]

OK, my bad, never heard of this before. Sounds cool.