Using digital output in single cycle timed loop on FPGA of cRIO

[MP10]

Hi everyone,

I am trying to create a clock signal of 100 kHz on FPGA of cRIO (NI cRIO 9025) with internal clock rate 40MHz using Single cycle timed loop. Inside the loop there is a digital output of one the module (NI 9403) which is connected to the FPGA target (block diagram VI snippet attached). During compilation I get an error stating that the digital output takes more than one tick of the clock, hence cannot be used in the single cycle timed loop (see attached picture error.PNG). However, in this video (time 2:28) made by NI Tutorials the guy has the digital output in the single cycle timed loop.

My question is: What should I do so that I can use the digital output in the single cycle timed loop? Or is there any other workaround to make the 100 kHz clock signal without using single cycle timed loop? I have tried normal while loop, but the max frequency I have got was around 75 kHz.

Thanks in advance for your answers.

MP10

[ZX81]

Different output devices vary.  The video writes to a modules discrete I/O channels, but I didn't see what module it was.  I only did a quick look, and didn't find 'CLK'.  Is that an alias to a module output (like Mod2Out3)?  Whatever the output is, you will need the documentation on it to be certain what you can do with it.

Even if you are able to write to an I/O in a single-cycle-timed-loop, that doesn't always mean the physical output updates that fast.  Especially with analog outputs.

Some I/O have configured clock options.  There might be a way to configure the module (or controller) to start the clock, instead of turning the bit on & off yourself.

minor optimization trick:  instead of counting up to the 'half cycle duty' value, count down from it.  Comparing to 0 takes almost no FPGA real-estate, but comparing to an arbitrary value can take a little (not much; this is only a tiny improvement).  You could also change the data type to U8; the fewer bits you use, the less FPGA gets used up.  Most FPGAs now are so huge, it isn't very important to optimize, but it does make compile times faster, too.

[MP10]

ZX81 thanks for your respons and the tricks.

Yes the CLK is an alias. I kind of hoped that the module can make it, but it seems it cannot. Will check the documentation.

[crossrulz]

The specification is quite clear that the 9403 can have a clock rate of up to 140kHz.  So a SCTL is out of the question here.  You could go with a normal While loop with a delay so that each iteration is at 200kHz (5us).

[MP10]

I have tried simple While loop with flat sequence and the delay, but the fastest I could make the loop run was approx. 75 kHz, see attached picture. Decreasing the half cycle duration below 7us led to no change in the frequency. I measured the duration of the while loop, going below the 7 us half cycle duration did not decrease the duration of the loop any further. So I cannot reach the iteration rate at 200 kHz...do not know why...