Using sample clock for hardware timing

[TuanTruong]

Hi Guys,

I'm working on a project where I'm using NI USB 6341 to create a pulse train with a frequency varies like sinusoidal fashion (The frequency will change according to the output of a sine function). I was able to do that but I use "wait" as a delay so the stepper motor can keep up with the clock. Now, I want to use the sample clock as timing instead of using "wait" because it's inaccurate. Does anybody have any idea how to do this? I'm still new to LabView and don't have that much experience.

Tuan Truong.

[Kevin_Price]

What is the overall application?  When you generate this variable-freq pulse train, what responds to it and why is it important for the frequency to vary sinusoidally?

There are a number of little subtleties you're liable to encounter in just the discrete math, before you even get to the code.

- since frequencies need to be positive, the sine wave pattern needs an offset so it will never be negative, 0, or nearly 0.  (A pulse of near-0 frequency would have too long a duration to maintain the desired sine wave modulation pattern)

- pulse trains are inherently discrete, leading to some further constraints / quirks like those mentioned below

- the minimum pulse train frequency should be considerably higher than the frequency of the sine wave that modulates it.  For example - pulse train freqs that vary from 100 to 200 Hz pulses according to a 10 Hz sine wave. 

- you'll find that more pulses are issued during the upper half of the sine wave than the lower half.  This is one of those discrete math artifacts.  The upper half of the sine wave contains the higher frequencies, which correspond to shorter intervals.  So you'll need more of those shorter intervals to make the upper half of the sine wave take the same total time as the lower half.

These things should make sense to you before you start writing code to implement it on your X-series DAQ device.  There you'll be looking to generate a buffered pulse train output.  It'll be easiest (but probably also more "quantized-looking") to advance through the buffer at a slower constant rate using an external sample clock (that you can generate with another counter).  It's also possible to use "Implicit" timing where you'd advance through the buffer at a variable rate dictated by each individual frequency value in the buffer.  However, it's much trickier to generate the data for this buffer while also making sure it represents exactly an integer number of sine wave cycles.

-Kevin P