VI communication, modeling bus architecture (newbie questions)

[mgenovese]

OK, I got the hint 🙂  Attached is the code, zipped up.  Two files - PBus Model (top-level), and Peripheral (the bus master).  Idea is that the peripheral was "instantiated" (sorry to keep using that word - only way I know to say it) twice in the PBus Model.  However, right now in the PBus Model Front Panel, if I run, I get an exception error.  But you can see how I am attempting to connect up the Peripheral master at the top level. 

The Peripheral master has a RX queue and TX queue, and some simple logic in between that is used to determine if the TX queue has elements in it, and to assert the requestor line.  There's a random number generator to determine whether to select doing a READ (use the RX queue for inbound data) or a WRITE (use the TX queue for sending outbound data).  However, I haven't really gotten that far in terms of implementation yet; just trying to get the basics to work right.

Thanks,

Matt
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[johnsold]

Matt,

I looked at your VIs. You have some problems with stopping. I modified things using functional globals so that when the top level panel Stop button is pressed, all the parallel loops also stop. I put the stop button in a while loop containing an event case. The last loop in the subVI (containing the Tx and Rx Request indicators will only execute once because it does not start until the other four loop have finished (think dataflow) and at that time the Stop global is true so the loop will stop after the first iteration.

I think what you are trying to do is quite interesting and quite achievable with LV. I think queues will be a very workable means of simulating the hardware port communication.

Lynn