VI of the Day (8/19/09)

[battler.]

Oh that's not wha NI teach in their training.  Sounds like race conditions to me.  What's the definition then?

Cheers.

[Ben]

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battler. wrote:

Oh that's not wha NI teach in their training.  Sounds like race conditions to me.  What's the definition then?

Cheers.

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I will not ask where you took that course. If you took it from one of the instructors I work with, you would have been told... 

A Race Condition is any circumstance where two entities attempt to define a single value without proper sequencing. A common construct in LV that leads to a Race Condition is two or more loops writting to the same local. The term can also extend beyond teh diagram to registers in a PLC etc.

Wiki has an entry on this topic if you want to read the generally accepted definition for this term ("I get all of my mis-information from the internet.")

RE: 0 ms wait.

It is LV short hand for "its OK to check if someone else want the CPU once every cycle". It is how LV VI play nice together.

Ben

Message Edited by Ben on 08-20-2009 08:23 AM

[SynergyMike]

Darin - What AnalogKid said.  I use Wait all the time to allow my GPIB instruments time to do whatever before going on to the next step.  I actually made a small VI with just Error In/Out and a Wait (with time to wait as an input).  I know there are operation complete and status things I could do instead, but for me it is simpler just to Wait instead of checking the GPIB constantly.

Regards,

Michael Tracy

Synergy Microwave

[Darin.K]

Hi Mike (and AK2DM), Great example, I have used my personal Visa VIs (which include my own wait subVI similar to the OpenG version) for so long that I forgot what was under the hood.  Just promise me that you don't use the stacked sequence to put the wait between the write and read.

Thanks for chiming in!