I am not certain about what is happening with your VI but something would make lots of sense.
I just posted this somewhere else, in case you're not familiar: In case you don't already know, once your code is
written using LabVIEW, to be able to run on the FPGA machine, it has to
be compiled, or even transformed, into a series of logic elements. The
process starts by tranforming the LabVIEW code into VHDL (or verilog, I
don't know which one they use) and then the Xilinx tool (company who
makes the FPGA) transform this file into a complex series of logic
operations (down to the level of AND and OR gate basically).
If you want to download the code again onto the board, it would make lots of sense to save all the work done on the HD to save yourself all the compile time the next time. My guess is that the VHDL file, the bit file (raw info downloaded to the FPGA) and other parts or results from the process are saved along the way. Hopefully someone from NI can let us know if it is true.
