Dear Professionals,
I hope you can help me with the following problem.
I have a linear CLink camera (Basler spL 4096−140km), which is connected to NI PXIe-7976R module (via NI 1483 Camera Link adapter), installed into PXIe-1095 chassis.
Camera is set to acquire a single line image on external (50 kHz) trigger.
After acquisition is done, pixel values are transmitted to the FPGA module (PXIe-7976R) in 4 pixels portions per single 80 MHz clock tick (the code is placed into a SCTL).
My goal is to apply a lowpass filter to the image while it is being transmitted and make a plot - Pixel value vs Pixel Index.
As I use IMAQ FPGA Camera Link 4 Tap 12-Bit.vi (standard Vision FPGA library), before proceeding to the next code step, the 8 pixels are accumulated.
So, in fact I have a transmission of 8 pixels on each second clock tick.
To design lowpass filter I used Digital Filter Design toolkit. So, with it I get a *.fds file (in a fixed point representation).
Afterwards, in FPGA project I use IP Generator, to generate a sub-vi, which I use then in my FPGA vi code.
In IP Generator I chose the above filter file to load (See Fig. 0) and then in "More Options" I use "Inside SCTL" and set Number of parallel data paths to 8 (Fig. 1).
So, I have the code and filter working (in general) but the resulting plot shows some regular beating after every 8 pixels (Fig. 2).
Do you have any idea, where this comes from? Which parameter I have to change?
Thank you very much in advance.
