Will,
Thanks for posting your question and congratulations on making your first post here in the discussion forums.
The question that you are asking about using a subVI both inside and outside of a timed loop is an interesting one. (When you try to do this, I believe you receive an error message indicating that you have callers both inside and outside of a timed loop and an error code of 61056). While you are correct that LabVIEW FPGA creates separate copies of code on the FPGA for reentrant VIs, the situation with calls both inside and outside of a timed loop will cause an error. The reason that this occurs is because LabVIEW FPGA strives to optimize code inside of a timed loop, and as a result uses different compilation methods for code inside and code outside the loop. In the case that you presented, you are using the same subVI in both locations, so LabVIEW would like to compile both of them the same way. However due to their placement, LAbVIEW would like to compile them differently, and as a result, an error occurs.
The workaround to this problem is simple. Simply create two identical VIs with different names. Use one of them inside the timed loop(s) and the other one outside of the loop(s), and you should have no problems.
I hope this helps to resolve the issue that you are having. If it doesn't please post back with some additional details about the problem that you are having so that this forum can help you to resolve this issues.
Best of luck with your FPGA application.
Regards,
Jed R.
Applications Engineer
National Instruments
