Why do I have to "kickstart" my cRIO 9103 Digital Output?

[mcsynth]

I have a cRIO system that I programmed as a diesel engine controller. I wrote a PC operator interface program, a cRIO-9004 RT control program, and the cRIO-9103 FPGA code, using one AI, one DI, and one DO module.

Before saving the RT program for compiling from the RT target, I always do a search for the FPGA board to be sure I'm targeted properly. I then compile and embed the startup.exe on the RT, and I also compile an executable on the PC platform from the same saved library.

When booting up the embedded program, it reads all the AI and DI inputs, does all the calculations, but does not create the output pulses to start the engine. Then I launch the PC compiled version, target it to the RT platform, wait for it to load, and it works fine. The embedded RT version and PC version were both compiled from the same Application Distribution code.

Embedded RT bootup has always worked for me in the past, even with PXI FPGA, but the cRIO is the first problem I've had with it.

Thanks for any help,
Mcsynth

[BoxTrooper]

Perhaps, your cRIO is simply not enabling the digital output. The cRIO has different VIs to write data to and enable the digital output. The digital output terminals must be "enabled" using a VI that does only that.
..
I do not have a DO module, but I just finished looking for this for my own purposes, I hope it helps, but I cannot test it.

[mcsynth]

I'm not aware of any specific enabling VI's other than the alias setup required in the Embedded Project Manager and the alias assignments in the FPGA code itself.

As I mentioned, it works properly when the compiled code is uploaded from a PC to the RT controller, and also when using the equivalent code in a PXI FPGA platform. THe only time it doesn't work is when the RT controller is powered up into the embedded Startup.exe. The PXI version booted up OK.

Could you attach an example of one of these enabling VI's?

Thanks,
Mcsynth

[Jeff M]

Hi mcsynth,

The enable VI that BoxTrooper was referring to in a previous post, is found in the Advanced FPGA Device I/O palette. To clear up any confusion, the main point is that "Digital Output" combines the use of "Digital Data" and "Digital Enable" into one function. So you are actually already enabling the data to be outputted, and using the Digital Enable function should not be necessary. Here are the function descriptions from LabVIEW Help:

DIGITAL OUTPUT:
Sets the state of the digital lines you specify in the Configure Digital Output dialog box. The Digital Output function both writes the data and enables the terminal for output. Double-click the Digital Output function on the block diagram to display the Configure Digital Output dialog box.

DIGITAL ENABLE:
Enables the Digital Data function to drive data from the FPGA on the digital lines you specify in the Configure Digital Enable dialog box. Use the Digital Data function to set the output data. The Digital Enable function receives Boolean inputs. FALSE disables the digital line. TRUE enables the digital line. Double-click the Digital Enable function on the block diagram to display the Configure Digital Enable dialog box.

DIGITAL DATA:
Writes data to the FPGA on the digital lines you specify in the Configure Digital Data dialog box without enabling the lines for output. You can use the Digital Enable function to enable the lines. Double-click the Digital Data function on the block diagram to display the Configure Digital Data dialog box.

I would like you to post a simplified version of your code to ftp.ni.com/incoming under the name "kickstart" so I can have a look. Also, please outline the exact steps you did in a little more detail, as I will try to reproduce this on my machine. Are your steps for targetting the CompactRIO exactly the same as the steps for targetting your PXI FPGA board? (they should be). Thanks and I look forward to testing this out for myself.

Regards,

Jeff M.

Applications Engineering
National Instruments