LV2017 (or some earlier versions) supports a great feature - do LabVIEW and HDL cosimulation with Questa Sim:
http://zone.ni.com/reference/en-XX/help/371599N-01/lvfpgahelp/fpga_debug_steps/
With this feature, we can debug a host VI testbench and an FPGA VI with CLIPs by cosimulation.
Unfortunately, LV2018 drops the cosimulation support. In LV2018, you can only stimulate a CLIP by VHDL testbench. Does it mean we can't debug a host VI testbench by cosimulation in LV2018 anymore? Is there any workaround?
